QG5000XSL9TH Datasheet, PDF (396/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Figure 6-1. Simplified TAP Controller Block Diagram
Testability
6.1.3
The TAP logic consists of a finite state machine controller, a serially-accessible
instruction register, instruction decode logic and data registers. The set of data
registers includes those described in the 1149.1 standard (the bypass register, device
ID register, and so forth.), plus Intel 5000X chipset-specific additions.
Accessing the TAP Logic
The TAP is accessed through an 1149.1-compliant TAP controller finite state machine,
which is illustrated in Figure 6-1. The two major branches represent access to either
the TAP Instruction Register or to one of the component-specific data registers. The
TMS pin controls the progress through the state machine. TAP instructions and test
data are loaded serially (in the Shift-IR and Shift-DR states, respectively) using the TDI
pin. A brief description of the controller’s states follows; refer to the IEEE 1149.1
standard for more detailed descriptions.
396
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet