QG5000XSL9TH Datasheet, PDF (107/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.4
3.8.8.5
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3, 0
0
0Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Ch
Intel 5000Z Chipset
4-7
0
0Ch
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RW
00h
CLS: Cache Line Size
This is an 8-bit value that indicates the size of the cache line and is specified in
DWORDs. It does not affect the MCH.
PRI_LT[7:2, 0] - Primary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the primary interface. It does not affect/influence PCI Express functionality.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
0Dh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Dh
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
0Dh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
Prim_Lat_timer: Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
BIST[7:2,0] - Built-In Self Test
This register is used for reporting control and status information of BIST checks within
a PCI Express port. It is not supported in the Intel 5000P Chipset MCH.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
107