QG5000XSL9TH Datasheet, PDF (19/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Introduction
Table 1-1.
General Terminology (Sheet 7 of 7)
Terminology
Transaction, Txn
Transmitter
Upstream
Description
An overloaded term that represents an operation between two or more agents that
can be comprised of multiple phases, cycles, or packets.
1. The Agent that sends a Packet across an interface regardless of whether it was
the original generator of the packet.
2. More narrowly, the circuitry required to drive signals onto the physical medium.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
1.2
Related Documents
1.3
Document
Dual-Core Intel^® Xeon^® Processor-Based Servers Platform Design
Guide
Dual-Core Intel^® Xeon^® Processor 5000 Sequence Thermal/Mechanical
Design Guideline
Intel^® 6402/6400 Advanced Memory Buffer Component External Design
Specification
Intel^® 631xESB/632xESB I/O Controller Hub Datasheet
Dual-Core Intel^® Xeon^® Processor 5000 Sequence Electrical,
Mechanical, and Thermal Specifications (EMTS).
Intel^® 5000 Series Chipsets MCH BIOS Specification
JEDEC FB-DIMM Memory Specification
PCI Local Bus Specification, Rev 2.3.
PCI Express Interface Specification, Rev 1.0a
Document Number/ Location
http://developer.intel.com/design/
http://developer.intel.com/design/
http://developer.intel.com/design/
http://developer.intel.com/design/
http://developer.intel.com/design
http://developer.intel.com/design
www.jedec.org
www.pcisig.org
www.pcisig.org
Intel^® 5000X Chipset Overview
Figure 1-1 shows an example block diagram of an Intel 5000X chipset-based platform.
The Intel 5000X chipset is designed for use in high performance workstations based on
the Dual-Core Intel Xeon Processor 5000 sequence. The Intel 5000X chipset supports
two processors on dual independent point to point system buses operating at 266 MHz
(1066 MTS) or two processors on dual independent point to point system buses
operating at 333 MHz (1333 MTS). The theoretical bandwidth of the two processor
busses is 17 GB/s for Dual-Core Intel Xeon 5000 series and 21GB/s for Dual-Core Intel
Xeon 5100 series.
Intel 5000X chipset features a high performance PCI Express* graphics port capable of
through puts of 4 GB/s. This graphics port contains several architectural enhancements
designed to optimize graphics performance in demanding video applications. One of the
architectural enhancements in Intel 5000X chipset is the inclusion of a Snoop Filter to
eliminate snoop traffic to the graphics port. Reduction of this traffic results in significant
performance increases in graphics intensive applications.
The Dual-Core Intel Xeon 5000 Series has a 2 MB L2 cache, a 266 MHz (1066 MTS)
system bus and Dual-Core Intel Xeon 5100 Series has a 4MB shared L2 cache, a
333MHz (1333 MTS) system bus. They are fabricated using a 65nm process in a
771-pin LGA package.
In a Intel 5000X chipset-based platform, the MCH provides the processor interface,
fully buffered DIMM memory interfaces, PCI Express bus interfaces, ESI interface, and
SM Bus interfaces.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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