QG5000XSL9TH Datasheet, PDF (189/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.13.16 NRECSF - Non-Recoverable Error Control Information of Snoop Filter
3.8.13.17 RECSF - Recoverable Error Control Information of Snoop Filter
Device:
Function:
Offset:
Version:
16
2
B0h
Intel 5000X Chipset
Bit
63:38
37
36:16
15:4
3
2
1:0
Attr
RV
ROST
ROST
ROST
ROST
ROST
ROST
Default
0h
0
0h
000h
0
0
00
Reserved
Hit(1), Miss(0)
Tag(A[39:19])
Set(A[18:7])
Interleave(A[6])
State
Presence Vector
Description
Device:
Function:
Offset:
Version:
16
2
B8h
Intel 5000X Chipset
Bit
63:38
37
36:16
15:4
3
2
1:0
Attr
RV
ROST
ROST
ROST
ROST
ROST
ROST
Default
0h
0
0h
000h
0
0
00
Reserved
Hit(1), Miss(0)
Tag(A[39:19])
Set(A[18:7])
Interleave(A[6])
State
Presence Vector
Description
3.8.13.18 FERR_FAT_INT - Internal First Fatal Error Register
FERR_FAT _INT latches the first MCH internal fatal error. All subsequent errors get
logged in the NERR_FAT_INT.
Device:
Function:
Offset:
Version:
16
2
C0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:5
RV
4
RWCST
3
RV
2
RWCST
1
RWCST
0
RWCST
000
Reserved
0
B7Err: Multiple ECC error in any of the ways during SF lookup
0
Reserved
0
B3Err: Coherency Violation Error for WEWB
0
B2Err: Multi-Tag Hit SF
0
B1Err: DM Parity Error
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
189