QG5000XSL9TH Datasheet, PDF (355/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Table 5-15. Options and Limitations (Sheet 2 of 2)
Parameter
Support
Power Management
No Cable Support & no repeaters
Poisoning
The MCH cannot be powered down, but will forward messages, generate
PME_Turn_Off and collect PME_TO_Acks. It will provide the PM Capabilities
structure. The MCH does not support Active State Power Management nor
the L0s state.
Retry buffers are sized to meet the Intel 5000X chipset platform
requirements for an integrated DP chassis and which do not require cable
or repeater support. Only an 8 inches of FR4 internal trace connector
latency is assumed.
MCH will poison data that it cannot correct
5.13.7 PCI Express Port Physical Layer Characteristics
The PCI Express physical layer implements high-speed differential serial signalling
using the following techniques:
• Differential signalling (1.6 V peak-to-peak)
• 2.5 GHz data rate (up to 2 GB/s/direction peak bandwidth for a x8 port)
• 8b/10b encoding for embedded clocking and packet framing
• Unidirectional data path in each direction supporting full duplex operation
• Random idle packets and spread-spectrum clocking for reduced EMI
• Loop-back mode for testability
• Lane reversal
• Polarity Inversion
Figure 5-21 illustrates the scope of the physical layer on a PCI Express packet. There
are two types of packets: Link layer packets and Transaction Layer Packets. The
physical layer is responsible for framing these packets with STP/END symbols
(Transaction Layer Packets) and SDP/END symbols (Data Link Layer packets). The
grayed out segment is not decoded by the Physical layer.
Figure 5-21. PCI Express Packet Visibility By Physical Layer
STP Link/Txn Layer Visible Info END
SDP Link Layer Visible Info END
5.13.7.1
PCI Express Training
To establish a connection between PCI Express endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. In the case of a x8 port,
the x4 link pairs will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or x4 link,
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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