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| QG5000XSL9TH Datasheet, PDF (203/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH) | |||
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Register Description
Table 3-41. FB-DIMM Host Data Cycle Valid Mux Select
FSB:Memory Frequency
Gear Ratio1
Value
333:333
1:1
267:267
400:400
333:267
5:4
00h
00h2
267:333
4:5 (conservative)
01h
267:333
4:5 (aggressive)
04h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
2. Ignored by Mgr registers in the 5:4 mode.
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
203
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