QG5000XSL9TH Datasheet, PDF (314/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
the copy has completed. This is accomplished autonomously by the memory control
subsystem. The SPCPS.SFO configuration bit is set and an interrupt is issued indicating
that a sparing event has completed.
Sparing cannot be invoked while operating a mirrored memory configuration. Sparing
to a smaller DIMM is not supported.
Note: DIMM sparing is not validated in the Single Channel Mode when Intel 5000P
Chipset.MCA.SCHDIMM is set.
5.3.4
Data Poisoning in Memory
Data Poisoning in memory is defined as all zeroes in the code word (32B0 except for
the least significant bytes being 0xFF00FF. The Intel 5000P Chipset MCH poisons a
memory location based on the events described in Table 5.5, “Memory Poisoned Table”
Table 5-5.
Memory Poisoning Table
Event
Correctable Error
UnCorrectable Error
Normal Memory
Read
Correct Data to be given register
Intel 5000P Chipset MCH logs M17 error.
(Correctable Non-Mirrored demand data
ECC Error)
Correct Data to be written back to
memory
Detects an Uncorrectable and logs a M9
error (Non-aliased uncorrectable non-
mirrored demand data ECC error)
Re-Issue Read to Memory
If error persistent
1. Poison the response to requester and log.
2. Leave data untouched in memory location
Patrol Scrub
Correct Data to be written back to
memory and log M20 error. (Correctable
patrolled data ECC error)
1. Log and Signal M12 Error (Non-Aliased
uncorrectable patrol data ECC error).
2: Leave data untouched in memory
location.
DIMM Spare Copy
Correct Data to be written back to
memory and log M19 error. (Correctable
re-silver or spare copy data ECC error)
If error persistent
1. Log and Signal M11 Error (Non Aliased
uncorrectable re-silver or spare copy data
ECC error).
2: Poison Location in DIMM Spare
Mirror Copy
Correct Data to be written to new
memory and log M19 error. (Correctable
re-silver or spare copy data ECC error)
Re-use Read to memory and signal a M11
error. (Non-aliased uncorrectable re-silver or
spare copy data ECC error).
If error persistent
1. Poison the new memory image.
5.3.5
Patrol Scrubbing
To enable this function, the MC.SCRBEN configuration bit must be set. The scrub unit starts at DIMM Rank
0 / Address 0 upon reset. Every 16k core cycles the unit will scrub one cache line and then increment the
address one cache line provided that back pressure or other internal dependencies (queueing, conflicts etc) do
not prolong the issuing of these transactions to FB-DIMM. Using this method, roughly 64GBytes of memory
behind the Intel 5000P Chipset MCH can be completely scrubbed every day (estimate). Error logs include
RAS/CAS/BANK/RANK. Patrol scrub writes hit both branches in mirrored mode (when MC.MIRROR is
set). Normally, one branch is scrubbed in entirety before proceeding to the other branch. In the instance of a
fail-down to non-redundant operation that off-lines the branch that was being scrubbed, the scrub pointer
merely migrates to the other branch without being cleared. In this unique instance, the scrub cycles for that
branch is incomplete.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet