QG5000XSL9TH Datasheet, PDF (256/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.3 CCR: Class Code Register
3.10.4
Device:
Function:
Offset:
Version:
8
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr
Default
Description
23:16 RWO 08h
Base Class Code: A 08H code indicates that the DMA engine device is a
peripheral device¹. A 06H code is used to indicate a Host bridge device.
Default: 08h
15:8 RWO 80h
Sub-Class Code: An 80H code indicates that the DMA engine device is a non-
specific peripheral device. A 00H code is used to indicate a Host bridge device.
Default: 80h
7:0
RWO 0h
Register-Level Programming Interface: This field identifies a default value
for non-specific programming requirements.
Notes:
1. A peripheral device in this case denotes an integrated device in the root complex.
The bits in this register are writable once by BIOS in order to allow the device to be
programmable either as an OS-visible device [088000h](implementing a driver) or a
chipset host bridge device [060000h] (relying on BIOS code and/or pure hardware
control for programming the DMA engine registers). The default value of the CCR is set
to 088000h (corresponding to an integrated device in the root port).
CB_BAR: DMA Engine Base Address Register
Device:
Function:
Offset:
Version:
8
0
10h
Intel 5000P Chipset
Bit Attr
Default
Description
63:40 RO
39:10 RW
9:4
RV
3
RO
2:1
RO
0
RO
0h
003F9C00h
0h
0
10
0
CB_BASE_Win_Upper: Upper DMABase Window:
The upper bits of the 64-bit addressable space are initialized to 0 as default
and is unusable in Intel 5000 Series Chipset.
CB_BASE_WIN: DMABase Window
This marks the 1KB memory-mapped registers used for the chipset DMA and
can be placed in any MMIO region (low/high) within the physical limits of the
system. For instance the Intel 5000P Chipset MCH uses only 40-bit
addressable space. Hence bits 39:10 are assumed to be valid and also contains
the default value of the CB_BAR in the FE70_0000h to FE70_03FFh range.
Reserved
Pref: Prefetchable
The DMA registers are not prefetchable.
Type: Type
The DMA registers is 64-bit address space and can be placed anywhere within
the addressable region of the Intel 5000 Series Chipset (up to 40-bits).
Mem_space: Memory Space
This Base Address Register indicates memory space.
This DMA Engine base address register marks the memory-mapped registers used for
the DMA functionality.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet