QG5000XSL9TH Datasheet, PDF (381/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.16.9
The compatible set of hot-plug registers may be accessed via memory-mapped
transactions, or via the Intel 5000X chipset MCH configuration mechanism as defined
in the configuration mechanism chapter of this document. For specific information on
the hot-plug register set, refer to the chapter on configuration register details.
The messages used for the hot-plug model are listed in Table 5-15, “PCI Express Hot-
Plug Interrupt Flow” on page 343 and Table 5-19, “MCH to Intel 631xESB/632xESB I/O
Controller Hub Port Configurations” on page 352 describe the behavior of the button
and LEDs.
Virtual Pin Ports
Shown in the Figure 5-1 is a high level block diagram of virtual pin ports and theoretical
maximum number of PCI Express card slots that could be supported for hot-plug
operations. In this VPP usage model, 16 slots (max) are shown in Figure 5-1 but for the
Intel 5000P Chipset Platform only 6 PCI Express slots¹ will be used for the I/O hot-plug
operations.
Note: Port 0, the ESI slot, is not hot-pluggable.
Since Intel 5000X chipset MCH has only six PCI Express ports, only six hot-plug slots
should be present in a Intel 5000X chipset MCH platform. Intel 5000X chipset MCH
PCI Express virtual pin port will only process six hot-plug slots accordingly.
1. This does not include the ESI (port 0) which is not hot-pluggable.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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