QG5000XSL9TH Datasheet, PDF (148/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11.7
PEXLNKCTRL[7:2, 0] - PCI Express Link Control Register
The PCI Express Link Control register controls the PCI Express Link specific parameters.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
7Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
7Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
7Ch
Intel 5000P Chipset
Bit
15:8
7
Attr
RV
RW
6
RW
5
WO
4
RW
3
RO
2
RV
Default
00h
0
0
0
0
0
0
Description
Reserved.
Ext_Synch: Extended Synch
This bit when set forces the transmission of 4096 FTS ordered sets in the L0s
state followed by a single SKP ordered set prior to entering the L0 state, and
the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the
Recovery state. This mode provides external devices (for example, logic
analyzers) monitoring the Link time to achieve bit and Symbol lock before the
Link enters the L0 or Recovery states and resumes communication.
CCCON: Common Clock Configuration
0: indicates that this PCI Express port and its counterpart at the opposite end
of the Link are operating with an asynchronous reference clock.
1: indicates that this PCI Express port and its counterpart at the opposite end
of the Link are operating with a distributed common reference clock.
Components utilize this common clock configuration information to report the
correct L0s and L1 Exit Latencies.
RLNK: Retrain Link
This bit, when set, initiates link retraining in the given PCI Express port. It
consistently returns 0 when read.
LNKDIS: Link Disable
This field indicates whether the link associated with the PCI Express port is
enabled or disabled.
0: Enables the link associated with the PCI Express port
1: Disables the link associated with the PCI Express port
Software should wait a minimum of 2 ms to make sure the link has entered
the electrical idle state before clearing this bit.
RCB: Read Completion Boundary
This field defines the read completion boundary for the PCI Express port.
Defined encodings for RCB capabilities are:
0: 64 byte
1: 128 byte
The Intel 5000P Chipset MCH supports only 64 B read completion boundary
and is hardwired to 0.
Reserved.
148
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet