QG5000XSL9TH Datasheet, PDF (350/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Note:
• Enterprise South Bridge Interface (ESI), Port 0
• General purpose ports, Port 2, Port 3,
There is no PCI Express port designated as Port 1.
The ESI port is the primary interface to the Intel 631xESB/632xESB I/O Controller Hub.
This interface can be paired with up to two of the PCI Express ports (Port 2 and Port 3)
to increase available bandwidth to the Intel 631xESB/632xESB I/O Controller Hub. The
Intel 5000X chipset MCH supports a high performance x16 graphics PCI Express port.
This port contains several architectural enhancements to increase graphics
performance.
The following sections describe the characteristics of each of these port classes in
detail.
5.13.1 Intel 5000X Chipset MCH PCI Express Port Overview
The Intel 5000X chipset MCH utilizes general purpose PCI Express high speed ports to
achieve superior I/O performance. The MCH PCI Express ports are compliant with the
PCI Express Interface Specification, Rev 1.0a.
A PCI Express port is defined as a collection of bit lanes. Each bit lane consists of two
differential pairs in each direction (transmit and receive) as depicted in Table 5-17.
Figure 5-17. x4 PCI Express Bit Lane
Rx
Tx
Rx
P _Tx
O
R
T ^Rx
Tx
Rx
Tx
AC coupling capacitors
LANE 0
AC coupling capacitors
LANE 1
AC coupling capacitors
LANE 2
AC coupling capacitors
LANE 3
Tx
Rx
Tx
Rx ^P
O
R
Tx _T
Rx
Tx
Rx
LINK (x4)
The raw bit-rate per PCI Express bit lane is 2.5 Gbit/s. This results in a real bandwidth
per bit lane pair of 250 MB/s given the 8/10 encoding used to transmit data across this
interface. The result is a maximum theoretical realized bandwidth on a x4 PCI Express
port of 1 GB/s in each direction.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet