QG5000XSL9TH Datasheet, PDF (202/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.12
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
2. Ignored by MGr registers in the 5:4 mode.
HOSTTOFBDGRCFG: Host to FB-DIMM Gear Ratio
Configuration
This register consists of eight nibbles of mux select data for the proper selection of
gearing behavior on the Host to FB-DIMM path (south bound).
Device:
Function:
Offset:
Version:
16
1
168h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:0
Attr
Default
Description
RWST
11111111h
HSTFBDGRMUX: Host to FB-DIMM Clock Gearing mux selector.
Eight nibbles of mux select for FSB/core to memory/DDR2 geared clock
boundary crossing phase enables.
Refer to Table 3-40 for the programming details.
Table 3-40. Host to FB-DIMM Gear Ratio Mux Select
FSB:Memory Frequency
Gear Ratio¹
Value
333:333
267:267
400:400
1:1
11111111h
333:267
5:4
00004323h
267:333
4:5 (conservative)
00023230h
267:333
4:5 (aggressive)
00023023h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
3.9.13 GRFBDVLDCFG: FB-DIMM Valid Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. It primarily affects the southbound data path for 4:5 gearing and
determines when a NOP packet is to be inserted into the FB-DIMM.
Device:
Function:
Offset:
Version:
16
1
16Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0 RWST
0h
FBDVLDMUX: FB-DIMM Data Valid Mux selector.
Determines which valid host cycle to insert NOP. Refer toTable 3-41 for the
programming details. This primarily affects the 4:5 gearing ratio.
202
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet