QG5000XSL9TH Datasheet, PDF (258/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.8.1
PMCAP - Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Device:
Function:
Offset:
Version:
8
0
50h
Intel 5000P Chipset
Bit
31:27
Attr
RO
26
RO
25
RO
24:22 RO
21
RO
20
RV
19
RO
18:16 RO
15:8 RO
7:0
RO
Default
11001
0
0
0h
0
0
0
010
58h
01h
Description
PMES: PME Support
Identifies power states which assert PMEOUT. Bits 31, 30 and 27 must be set
to '1' for PCI-PCI bridge structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power Management Interface
Specification Revision 1.1.
XXXX1b - PMEOUT can be asserted from D0
XXX1Xb - PMEOUT can be asserted from D1 (Not supported by Intel 5000P
Chipset MCH)
XX1XXb - PMEOUT can be asserted from D2 (Not supported by Intel 5000P
Chipset MCH)
X1XXXb - PMEOUT can be asserted from D3 hot
1XXXXb - PMEOUT can be asserted from D3 cold
D2S: D2 Support
The Intel 5000P Chipset MCH does not support power management state D2.
D1S: D1 Support
The Intel 5000P Chipset MCH does not support power management state D1.
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
PMECLK: PME Clock
This field is hardwired to 0h.
VER: Version
This field is set to 2h as version number from the PCI Express 1.0
specification.
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
1. When software initiates an S0 => S3 transition, it should make the DMA engine device to enter
D3 before completing the power management handshake with the MCH.
258
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet