QG5000XSL9TH Datasheet, PDF (49/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
.
Table 3-1. Configuration Address Bit Mapping
Source/
Destination
Bus
Device
Function
Dword
Offset
[11:8]
[5:0]
Byte in
Dword
Type
PCI Express Config Destination
Txns (including
ESI)
Bus[7:0]
Device[4:0] Function[2:0 Extended
]
Register
Addr[3:0]
Register
[5:0]
1st DW
BE[3:0]
Fmt,
Type
PCI Express
MMCFG
on FSB
Source
A[27:20]
A[19:15]
A[14:12]
A[11:8]
A[7:3]
BE[7:0]
n/a
BE[7:4]
PCI Express
MMCFG
from ESI or PCI
Express
Not permitted to access MCH or FB-DIMM regs and will be master aborted.
CPU/Inbound
Source
0
8
1
CB_BAR MMIO
Access
A[11:8]
A[7:3]
BE[7:0]
n/a
BE[7:4]
CFGADR Register Source
Bus Number DeviceID
[7:0]
[4:0]
Function
not present Register
Number[2:0]
Address
[5:0]
Not present n/a
CFC on
FSB
Source
CFGADR Register, see row above
BE[7:4]
n/a
JTAG Config Access Source
Bus Number DeviceID
Function
Extended Register
Register
n/a
[7:0]
[4:0]
Number[2:0] Register
Address[7:2 Address
Addr[3:0] ]
[1:0]
SMBus Config
Access
Source
Bus Number Dev[4:0]
[7:0]
Func[2:0]
Reg
Number
[11:8]
Reg[7:2]
command, n/a
Register
Number
Fixed MCH Memory Source
0
Mapped on FSB
16
0
cannot
access
A[15:10]
All accesses n/a
are 4 byte
MCH Register
Decoding
FB-DIMM Config
Cmds
Destination 00000000 See Table Function[2:0 Dword
Dword
Byte[3:0] n/a
14-4
]
Offset[9:6] Offset[5:0]
Destination A[23:15]
always 0
See Note¹
Cannot
access
A[7:3]
BE[7:0]
n/a
BE[7:4]
Notes:
1. These accesses are used to select channel/DIMM based on the AMBASE register.
3.4.1
Device Identification for Intel 5000P Chipset, Intel 5000Z
Chipset, and Intel 5000V Chipset Components
All devices in the Intel® 5000X chipset MCH reside on Bus 0. The following table
describes the root device ID for different MCH versions.
Table 3-2. Memory Control Hub ESI Device Identification
Component
Intel 5000P Chipset
Intel 5000Z Chipset
Intel 5000V Chipset
Register Group
DID
Enterprise South Bridge Interface
Enterprise South Bridge Interface
Enterprise South Bridge Interface
25C8h
25D0h
25D4h
Device
Functio
n
0
0
0
0
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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