QG5000XSL9TH Datasheet, PDF (147/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
78h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
78h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
78h
Intel 5000P Chipset
Bit
11:10
9:4
3:0
Attr
RO
RO
RO
Default
Description
01
if (port
0,1,3,5,7)
{x4} elseif
(port 2,6)
{x8} elseif
(port 4)
{x16} endif
0001
ACTPMS: Active State Link PM Support
This field indicates the level of active state power management supported on
the given PCI Express port.
00: Disabled
01: L0s Entry Supported
10: Reserved
11: L0s and L1 Supported
The Intel 5000P Chipset MCH does not initiate L0s active state Power
Management but it does permit a downstream device from placing the link in
L0s
MLW: Maximum Link Width
This field indicates the maximum width of the given PCI Express Link
attached to the port.
000001: x1
000100: x4
001000: x8
010000: x16
Others - Reserved
See Table 3-35.
MLS: Maximum Link Speed
This field indicates the maximum Link speed of the given PCI Express port.
0001: 2.5 Gb/s
Others - Reserved
Table 3-35. Maximum Link Width Default Value for Different PCI Express Ports
Device/Port
0,3,5,7
2,6
4
Maximum Link Width
x4
x8
x16
x8
Value
000100
001000
010000
001000
Table 3-35 shows various combining options for PCI Express ports. When ports
combine, the control registers for the combined port revert to the lower numbered
port. Thus when ports 2 and 3 are combined, the combined x8 port is accessed through
port 2 control registers.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
147