QG5000XSL9TH Datasheet, PDF (390/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Table 5-31. Intel 5000X chipset Error List (Sheet 3 of 7)
ERR #
in MCH
Error Name
IO6
PCI Express -
Completion
Time-out
IO7
PCI Express -
Completer
Abort
IO8
PCI Express -
Unexpected
Completion
Error
Definition
Pending transaction was
ACKed in the data link layer
but not within the time
limit.
Received return CA status
for horrible error on the
component. This is
equivalent to a target abort
on PCI.
Received a Completion
RequestorID that matches
the requestor but the Tag
does not match any
pending entries.
Error
Type
Log Register
Default=
UnCorr
(Check
UNCERR
SEV)
Default=
UnCorr
(Check
UNCERR
SEV)
Default=
UnCorr
(Check
UNCERR
SEV)
Log PEX_FAT_FERR/NERR
or PEX_NF_COR_FERR/
NERR based on their
respective Error types and
Severity (UNCERRSEV)
Log RPERRSTS for IO1,
IO11 and IO17.
Log UNCERRSTS for their
respective Error Types.
Log the first error pointer
for UNCERRSTS in
AERRCAPCTRL.
Log CORRERSTS for their
respective Error Types.
Log PEXDEVSTS for IO12
and other I/O errors based
on UNCERSEV
IO9
PCI Express - Received a transaction layer Default=
Malformed TLP packet that does not follow UnCorr
the TLP formation rules.
(Check
UNCERR
SEV)
IO10
PCI Express -
Receive Buffer
Overflow Error
Receiver gets more data or
transactions than credits
allow.
Default=
Fatal
(Check
UNCERR
SEV)
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
PCI Express -
Received
NonFatal Error
Message
MCH received a NonFatal
error message from the
south bridge.
PCI Express - Log header of packets with
Receiver Error errors
PCI Express -
Bad TLP Error
Received bad CRC or a bad
sequence number in a
transport layer packet.
PCI Express - Received bad CRC in a data
BAD DLLP
link layer packet.
PCI Express -
Replay_Num
Rollover
Replay maximum count for
the Retry Buffer has been
exceeded.
PCI Express -
Replay Timer
Time-out
Replay timer timed out
waiting for an Ack or Nak
DLLP.
PCI Express -
Received
Correctable
Error Message
MCH received a correctable
error message from the
south bridge.
ESI reset time-
out
Did not receive ESI
CPU_Reset_Done_Ack or
CPU_Reset_Done_Ack_Secr
ets messages within T_10max
after assertion of processor
RESET# while PWRGOOD
was asserted
UnCorr
Corr
Corr
Corr
Corr
Corr
Corr
Fatal
Log PEX_FAT_FERR/NERR
Cause / Actions
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Log header of packets with
errors
Log header of packets with
errors
Log header of packets with
errors
Log header of packets with
errors
Log header of packets with
errors
Log header of packets with
errors
Deassert processor RESET#.
Necessary to prevent
processor thermal runaway.
390
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet