QG5000XSL9TH Datasheet, PDF (98/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.5.6
3.8.6
3.8.6.1
3.8.6.2
BOFL[3:0] - Boot Flag Register
These registers can be used to select the system boot strap processor or for other cross
processor communication purposes. When this register is read, the contents of the
register is cleared. Therefore, a processor that reads a non-zero value owns the
semaphore. Any value can be written to this register at any time.
An example of usage would be for all processors to read the register. The first one that
gets a non-zero value owns the semaphore. Since the read clears the value of the
register, all other processors will see a zero value and will spin until they receive further
notification. After the winning processor is done, it writes a non-zero value of its choice
into the register, arming it for subsequent uses. These registers are also aliased to fixed
memory I/O addresses.
Device:
Function:
Offset:
Version:
16
0
C0h, C4h, C8h, CCh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:0
Attr
RCW
Default
Description
A5A5A5A5h SemaVal: Semaphore Value
Can be written to any value. Value is cleared when there is a read.
Control and Interrupt Registers
PROCENABLE: Processor Enable Global Control
The two FSBEN bits are used to enable or disable frontside bus arbitration. When
frontside bus arbitration is disabled the processor is effectively disabled.
Device: 16
Function: 0
Offset: F0h
Bit
31:5
4:3
Attr
RV
RWST
2
RWST
1:0
RV
Default
3fAh
11
0
0h
Description
Reserved.
FSBEN: FSB1 and FSB0 Enable
The field is defined as the following:
00: reserved
01: FSB1 is disabled. FSB0 is enabled.
10: FSB1 is enabled. FSB0 is disabled.
11: FSB1 is enabled. FSB0 is enabled. (default)
Hard-reset is needed after changing value in this register.
SFBYPASS: Snoop Filter Bypass
0: SF is enabled
1: SF is disabled
Note: The output of the fuse “SF CHOP” is gated appropriately with this
register field viz. SFBYPASS for further internal decoding by Intel 5000X
Chipset MCH. The fuse has overriding effect.
Reserved.
FSBS[1:0] - Processor Bus Status Register
This register holds status from the Processor Busses.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet