QG5000XSL9TH Datasheet, PDF (186/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.13.9
.
NRECADDRL[1:0]: Non Recoverable FSB Address Low Error Log
Register
This register captures the lower 32 bits of the FSB address for non recoverable errors
when a fatal error is logged in its corresponding FERR_FAT_FSB Register. This register
is only valid for Request FSB Errors.
Device:
Function:
Offset:
Version:
16
0
48Ch, 18Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:4
3
2:0
Attr
ROST
ROST
RV
Default
0h
0
000
Description
A31DT4: FSB Address [31:4]
A3: FSB Address [3]
Reserved
3.8.13.10 NRECADDRH[1:0]: Non Recoverable FSB Address High Error Log
Register
This register captures the upper 8 bits of the FSB address for non recoverable errors
when a fatal error is logged in its corresponding FERR_FAT_FSB Register. This register
is only valid for Request FSB Errors.
.
Device:
Function:
Offset:
Version:
16
0
490h, 190h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0
ROST
00h
A39DT32: FSB Address [39:32]
3.8.13.11 EMASK_FSB[1:0]: FSB Error Mask Register
A ‘0’ in any field enables that error.
Device:
Function:
Offset:
Version:
16
0
492h, 192h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15:9
8
7
6
5
4
3
2
1
0
Attr
RV
RWST
RWST
RWST
RWST
RV
RV
RV
RWST
RWST
Default
0h
1
1
1
1
0h
0h
0h
1
1
Description
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
186
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet