QG5000XSL9TH Datasheet, PDF (47/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.3
3.3.1
3.3.2
Routing Configuration Accesses
Intel® 5000X chipset MCH supports both PCI Type 0 and Type 1 configuration access
mechanisms as defined in the PCI Local Bus Specification, Revision 2.3. PCI Revision
2.3 defines hierarchical PCI busses. Type 0 configuration access are used for registers
located within a PCI device that resides on the local PCI bus. That is, the PCI bus the
transaction is initiated on. Type 0 configuration transactions are not propagated beyond
the local PCI bus. Type 0 configuration transactions must be claimed by a local device
or master aborted.
Type 1 configuration accesses are used for devices residing on subordinate PCI buses.
i.e Devices that are connected via PCI-to-PCI bridges. All targets except PCI-to-PCI
bridges ignore Type 1 configuration transactions. PCI-to-PCI bridges decode the bus
number information in Type 1 transactions. It the transaction is targeted to a device
local to the PCI-to-PCI bridge it is translated into a Type 0 transaction and issued to the
device. If the transaction is targeted to a bus subordinate (behind) to PCI-to-PCI
bridge, it passed through unchanged. Otherwise the Type 1 transaction is dropped.
Accesses to non operational or non existent devices are master aborted. This means
that writes are dropped and reads return all 1’s.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that supports up to 32 devices.
Each device is allowed to contain up to eight functions with each function containing up
to 256, 8-bit configuration registers. The PCI specification defines two bus cycles to
access the PCI configuration space: Configuration Read and Configuration Write.
Memory and I/O spaces are supported directly by the processor. Configuration space is
supported by a mapping mechanism implemented within the MCH. The PCI 2.3
specification defines the configuration mechanism to access configuration space. The
configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O
address 0CF8h through 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
through 0CFFh). To reference a configuration register a DWord I/O write cycle is used
to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that
bus, the function within the device, and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be set to 1b, to enable a
configuration cycle. CONFIG_DATA then becomes a window into the four bytes of
configuration space specified by the contents of CONFIG_ADDRESS. Any read or write
to CONFIG_DATA will result in the MCH translating the CONFIG_ADDRESS into the
appropriate configuration cycle.
The MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration
registers.
PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a device on PCI Bus 0.
The ESI bridge entity within the MCH is hardwired as Device 0 on PCI Bus 0. The ESI
bridge passes PCI south bridge configuration requests to the south bridge.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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