QG5000XSL9TH Datasheet, PDF (178/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
158h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
158h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
158h
Intel 5000P Chipset
Bit
31:18
17
16
15
14
13
12
11
10
Attr
RV
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
9
RWCST
8
RWCST
7
RWCST
6
RWCST
5
RWCST
4
RWCST
3
RWCST
2
RWCST
1
RWCST
0
RWCST
Default
0h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
First_NFAT_Corr_Err_IO19: Surprise Link Down (uncorrectable)
First_NFAT_COR_Err_IO17: PEX - Received Correctable Error Message
First_NFAT_COR_Err_IO16: PEX - Replay Timer Timeout (correctable)
First_NFAT_COR_Err_IO15: PEX - Replay_Num Rollover (correctable)
First_NFAT_COR_Err_IO14: PEX - BAD DLLP Error (correctable)
First_NFAT_COR_Err_IO13: PEX - Bad TLP Error (correctable)
First_NFAT_COR_Err_IO12: PEX - Receiver Error (correctable)
First_NFAT_COR_Err_IO11: PEX - Received Non Fatal (uncorrectable)
Error Message
First_NFAT_COR_Err_IO10: PEX - Receive Buffer Overflow Error
(uncorrectable)
First_NFAT_COR_Err_IO9: PEX -Malformed TLP (uncorrectable)
First_NFAT_COR_Err_IO8: PEX - Unexpected Completion Error
(uncorrectable)
First_NFAT_COR_Err_IO7: PEX - Completer Abort (uncorrectable)
First_NFAT_COR_Err_IO6: PEX - Completion Timeout (uncorrectable)
First_NFAT_COR_Err_IO5: PEX - Flow Control Protocol Error
(uncorrectable)
First_NFAT_COR_Err_IO4: PEX - Poisoned TLP (uncorrectable)
First_NFAT_COR_Err_IO3: PEX - Training Error (uncorrectable)
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
First_NFAT_COR_Err_IO2: PEX - Received Unsupported Request
(uncorrectable)
First_NFAT_COR_Err_IO0: PEX - Data Link Layer Protocol Error
(uncorrectable)
3.8.12.26 PEX_FAT_NERR[7:2, 0] - PCI Express Next Fatal Error Register
This register records the subsequent occurrences after the first unmasked PCI Express
FATAL errors and written by the MCH if the respective bits are set in the PEX_FERR_FAT
register.
178
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet