QG5000XSL9TH Datasheet, PDF (207/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Table 3-45. Optimum TREF values as a function of core: FBD gear ratios (in FBD Super
frames)
DIMM
DDRII533
DDRII667
Optimum TREF values as a function of core: FBD gear ratios
(in FBD Super frames)
1:1
5:4
4:5
6
6
N/A
7
N/A
8
3.9.19
DRTB - DDR Timing Register B
This register defines timing parameters that work with all DDR ports in the memory
subsystem. This register must be set to provide timings that satisfy the specifications
of all detected DDR ports. For example, if DDR ports have different TR2Ws, the
maximum should be used to program this register.
Device:
Function:
Offset:
Version:
16
1
4Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:19
18:16
15:12
11:8
7:4
3:0
Attr
RV
RW
RW
RW
RW
RW
Default
Description
000h
0h
0h
0h
0h
0h
Reserved
TW2RDR: Write command to read command delay, different rank
This parameter is the minimum delay from a write command to a read command on
different ranks of the same DIMM. This parameter prevents data strobe protocol
violations on the DIMMs DDR data bus. This parameter is defined in core cycles.
This parameter is dependent on cache line size. The formula for this value is BL/2 +
t_FRR - 1. t_FRR is the turnaround time required to read from different ranks on the
DIMM.
TR2W: Read command to write command delay
This parameter is the minimum delay from a read command to a write command on
the same DIMM. This parameter prevents data strobe protocol violations on the
DIMMs DDR data bus. This parameter is defined in core cycles. This parameter is
dependent on cache line size. The formula for this value is BL/2 + t_FRR + 1. t_FRR is
the turnaround time from read to write on the DIMM. This value applies to a DIMM-
hit in the conflict checking unit.
TW2R: Write command to read command delay, same rank
This parameter is the minimum delay from a write command to a read command on
the same rank. This parameter prevents data strobe protocol violations on the
DIMMs DDR data bus. This parameter is defined in core cycles. This parameter is
dependent on cache line size. The formula for this value is t_CL - 1 + BL/2 + t_WTR.
TR2R: Read command to read command delay
This parameter is the minimum delay from a read command to another read
command on a different rank of the same DIMM. This parameter prevents data
strobe protocol violations on the DIMMs DDR data bus. This parameter is defined in
core cycles. The formula for this value is BL/2 + t_FRR. t_FRR is the turnaround time
required to read from different ranks on the DIMM.
TW2W: Write command to write command delay
This parameter is the minimum delay from a write command to another write
command on the same DIMM. This parameter prevents data strobe protocol
violations on the DIMMs DDR data bus. This parameter is defined in core cycles.
This parameter is dependent on cache line size.The formula for this value is BL/2.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
207