QG5000XSL9TH Datasheet, PDF (196/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.2
Device:
Function:
Offset:
Version:
16
1
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr Default
Description
5
RW
4
RWC
3:0
RV
0
ERRDETEN: Error Detection Enable
‘1’ = Northbound CRC/ECC checking enabled.
‘0’ = Northbound CRC/ECC checking disabled
FB-DIMM “Alert” detection is disabled, status packets are ignored, northbound error
logging and data poisoning are disabled when Northbound CRC/ECC checking is
disabled.
0
SCRBDONE: Scrub Complete
The scrub unit will set this bit to ‘1’ when it has completed scrubbing the entire
memory. Software should poll this bit after setting the Scrub Enable (SCRBEN) bit
to determine when the operation has completed. If the Scrub enable bit is cleared
midway during the scrub cycle, then the SCRBDONE bit will not be set and the Intel
5000P Chipset MCH will stop the scrub cycle immediately.
0h Reserved
GBLACT - Global Activation Throttle Register
This register contains the hostel limit for Global Activation throttle control.
Device:
Function:
Offset:
Version:
16
1
60h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr Default
Description
7:0
RW
0
GBLACTLM: Global Activation Throttle Limit
This field controls the activation of Global throttling based on the number of
activates sampled per DIMM pair on each branch.
If the number of activates in the global throttling window¹ exceeds the number
indicated by the GBLACTLM filed in this register, then global throttling is started by
setting the THRSTS[1:0].GBLTHRT bit for the respective branch and the Global
activation throttling logic to use the THRTMID register for throttling.
The granularity of this field is 65536 activations. Refer to Table 3-37
If Software sets this value greater than 168, the chipset will cap the GBLACTLM
field to 168.
Notes:
1. If (MC.GTW_MODE==1), then the global throttling window is 4*1344 cycles (debug, validation). Else if
(MC.GTW_MODE==0), then the window is set to 16384*1344 cycles (normal).
Table 3-37. Global Activation Throttling as a Function of Global Activation Throttling Limit
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields
GBLACT.GBLACTM
Range (0.168)
0
1
2
16
32
64
Number of Activations
MC.GTW_MODE=0
(16384*1344 window)
No Throttling
(unlimited activations)
65536
131072
1048576
2097152
4194304
MC.GTW_MODE=1
(4*1344 window)
No Throttling
(unlimited activations)
16
32
256
512
1024
196
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet