QG5000XSL9TH Datasheet, PDF (292/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
4.4.2.1
Access to SMM Space (Processor Only)
Accesses to SMM space are restricted to processors, inbound transactions are
prohibited. Inbound transactions to enabled SMM space are not allowed and
Intel 5000X chipset MCH will set Intel 5000P Chipset MCH.EXSMRAMC.E_SMERR bit.
The following table defines when a SMM range is enabled. All the enable bits:
G_SMRAME, H_SMRAM_EN, and TSEG_EN are located in the Intel 5000P Chipset
MCH.EXSMRC register.
Table 4-7. Enabled SMM Ranges
Global Enable High SMM Enable TSEG Enable Legacy SMM
G_SMRAME
H_SMRAM_EN
TSEG_EN
Enabled?
0
X
X
No
1
0
0
Yes
1
0
1
Yes
1
1
0
No
1
1
1
No
HIGH SMM
Enabled?
No
No
No
Yes
Yes
Extended
SMRAM Space
(TSEG)
Enabled?
No
No
Yes
No
Yes
The processor bus has a SMMEM# signal that qualifies the request asserted as having
access to a system management memory. The SMM register defines SMM space that
may fall in one of three ranges: legacy SMRAM, Extended SMRAM Space (TSEG), or
High SMRAM Space (H_SMM). Table 4-8 defines the access control of SMM memory
regions from processors.
Table 4-8.
SMM Memory Region Access Control from Processor
G_SMRAME D_LCK D_CLS
D_OPEN
SMMEM#
Code Access to
SMM Memory¹
Data Access to
SMM Memory²
0³
x
x
x
x
no
no
1
0
x
0
0
no
no
1
0
0
0
1
yes
yes
1
0
0
1
x
yes
yes
1
0
1
0
1⁴
x
1
1
1
yes
no (legacy SMM)
yes (H_SMM,
TSEG)
x
illegal settings
illegal settings
1
1
0
x
0
no
no
1
1
1
0
0
no
no
1
1
0
x
1
yes
yes
1
1
1
0
1
yes
no (legacy SMM)
yes (H_SMM,
TSEG)
Notes:
1. BRLC
2. Data access transaction other than BRLC
3. For access to TSEG region (address range between ESMMTOP - TSEG_SZ and ESMMTOP), Intel 5000P Chipset
MCH will route to identical system memory by definition (as TSEG is not enabled).
4. It is a programming error if D_CLS and D_OPEN are both set to 1, Intel 5000P Chipset MCH’s
behavior is undefined. Intel 5000P Chipset MCH could master abort SMM access.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet