QG5000XSL9TH Datasheet, PDF (262/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.12 MSIAR: Message Signalled Interrupt Address Register
Device:
Function:
Offset:
Version:
8
0
5Ch
Intel 5000P Chipset
Bit
31:20
Attr
RO
19:12 RW
11:4 RW
3
RW
2
RW
1:0
RV
Default
FEEh
0h
0h
0
0
00
Description
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
AEXDSTID: Address Extended Destination ID
This field is not used by IA32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
ADM: Address Destination Mode
0: physical
1: logical
Reserved.
Not used since the memory write is D-word aligned
3.10.13 MSIDR: Message Signalled Interrupt Data Register
Device:
Function:
Offset:
Version:
8
0
60h
Intel 5000P Chipset
Bit
31:16
15
14
Attr
RV
RW
RW
Default
Description
0000h
0h
0h
Reserved.
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
LVL: Level
if TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages.
13:11 RW
For level triggered interrupts, this bit reflects the state of the interrupt input
if TM is 1h, then:
0: Deassert Messages
1: Assert Messages
0h These bits are don’t care in IOxAPIC interrupt message data field specification.
262
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet