QG5000XSL9TH Datasheet, PDF (134/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.10
3.8.10.1
PCI Express Message Signaled Interrupts (MSI) Capability
Structure
Message Signaled Interrupts (MSI) is an optional feature that enables a device to
request service by writing a system-specified message to a system-specified address in
the form of an interrupt message. The transaction address (for example, FEEx_xxxxh)
specifies the message destination and the transaction data specifies the message. The
MSI mechanism is supported by the following registers: the MSICAPID, MSINXPTR,
MSICTRL, MSIAR and MSIDR register described below.
MSICAPID[7:2, 0] - MSI Capability ID
3.8.10.2
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
58h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
58h
Intel 5000Z Chipset
4-7
0
58h
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
05h
CAPID: Capability ID
Assigned by PCI-SIG for message signaling capability.
MSINXPTR[7:2, 0]- MSI Next Pointer
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
59h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
59h
Intel 5000Z Chipset
4-7
0
59h
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
6Ch
NXTPTR: Next Pointer
This field is set to 6Ch for the next capability list (PCI Express capability
structure - PEXCAP) in the chain.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet