QG5000XSL9TH Datasheet, PDF (250/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.25.19 FBD[3:2]IBPATBUF2: FB-DIMM Intel IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in Intel IBIST operations.
Device: 22
Function: 0
Offset: 2A4h, 1A4h
Bit Attr
Default
31:24 RV
0
23:0 RWST 02CCFDh
Description
Reserved
IBPATBUF: Intel IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
3.9.25.20 FBD[1:0]IBPATBUF2: FB-DIMM Intel IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in Intel IBIST operations.
Device: 21
Function: 0
Offset: 2A4h, 1A4h
Bit Attr
Default
31:24 RV
0
23:0 RWST 02CCFDh
Description
Reserved
IBPATBUF: Intel IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
3.9.25.21 FBD[3:2]IBTXPAT2EN: Intel IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when Intel IBIST operations are
activated.
Device: 22
Function: 0
Offset: 2A8h, 1A8h
Bit
31:14
Attr
RV
Default
0h
13:10 RWST
Fh
9:0 RWST
3FFh
Description
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
3.9.25.22 FBD[1:0]IBTXPAT2EN: Intel IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when Intel IBIST operations are
activated.
250
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet