QG5000XSL9TH Datasheet, PDF (337/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.6.3.2
3. Logical APIC ID (LOGID)
4. Processor physical APIC ID (PHYSID)
The XTPR registers are modified by a front side bus xTPR_Update transaction. In
addition, the XTPR registers can be modified by software.
In addition, XTPR0 also contains a bit for Global Cluster Mode bit used in redirection of
logical destination mode messages. This bit indicates to the Intel 5000X chipset MCH
that destination field of the message is “flat” or physical (note that the XAPIC message
indicates whether the destination mode is physical or logical). The default logical mode
at reset is “flat” and must not be changed to “cluster” mode. Cluster mode is not
supported by the Intel^® 5000X Chipset.
More details on the Intel 5000P Chipset XTPR registers are described in the XTPR
register definition in Section 3.8.6.3.
The XTPR special cycle must guarantee that the XTPR register is updated for interrupt
redirection in a consistent manner. For reproducibility, there needs to be an internal
serialization point after which subsequent interrupts will be redirected based on the
updated XTPR value.
Redirection Algorithm
Redirection is performed if an interrupt redirection hint bit (A[3]) is set. This is the
algorithm used in determining the processor that the interrupt will be redirected to.
1. If A[3] =1, then this is a redirection (also known as “lowest priority”) interrupt
request. Proceed to the next step.
2. FLAT: If Destination Mode = 1 (A2 for I/O, Ab5 for IPIs) is disabled (0) in the XTPR,
then this is Flat-Logical Destination Mode. (Otherwise, proceed to the next step). To
select the arbitration pool, for each XTPR register: Note: Cluster Mode is not
supported and should always be disabled.
If (A[19:12] (DID) AND XTPR[n].LOGID[7:0]) > 0h
AND XTPR[n].TPREN =1
then XTPR[n] is included in the arbitration pool.
3. PHYSICAL: If Destination Mode = 0 (A2 for I/O, Ab5 for IPIs), then this is Physical
Destination Mode. All enabled xTPR’s are included in the arbitration pool.
4. If there are no xTPR’s in the arbitration pool, then forward to FSB with A[3]=0, but
otherwise “without modification”. Otherwise, continue to the next step.
5. XTPRs in the pool are categorized into 4 priority buckets depending on the priority.
The priority bucket levels are defined by register bits BUCKET(0-2)_LIM in the
REDIRCTL register.
If (0 <= XTPR.PRIORITY < BUCKET0_LIM) then priority bucket = 0
If (BUCKET0_LIM <= XTPR.PRIORITY < BUCKET1_LIM) then priority bucket =
1
If (BUCKET1_LIM <= XTPR.PRIORITY < BUCKET2_LIM) then priority bucket =
2
If (BUCKET2_LIM <= XTPR.PRIORITY < 16) then priority bucket = 3
6. All xTPR’s in the arbitration pool are compared. The xTPR register with the lowest
priority bucket value (0=lowest, 3=highest) is the “winner”.
7. If more than one xTPR register in the arbitration pool has the same lowest priority
bucket value, then LRU arbitration logic will pick an xTPR that was not recently
picked.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
337