QG5000XSL9TH Datasheet, PDF (370/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.16.2.4
Position
7:5
4:0
Configuration Register Mode Description
Memory Mapped Mode Description
Ignored.
Bus Number. Must be zero: the SMBus port
can only access devices on the MCH and all
devices are bus zero.
Memory map region to access.
01h = DMA
08h = DDR
09h = CHAP
Others = Reserved
Address Byte 2 Field
This field indicates the Device Number and Function Number of the desired
configuration register if for a configuration type access, otherwise it should be set
to zero.
5.16.2.5
Position
Configuration Register Mode Description
Memory Mapped Mode Description
7:3
Device Number. Can only be devices on the MCH. Zeros used for padding.
2:0
Function Number.
Address Byte 1 Field
This field indicates the upper address bits for the 4K region specified by the
register offset. Only the lower bit positions of this field are used, the upper four bits
are ignored.
5.16.2.6
Position
Description
7:4
Ignored.
3:0
Extended Register Number. Upper address bits for the 4K region of register offset.
Address Byte 0 Field
This field indicates the lower eight address bits for the register with the 4K region,
regardless whether it is a configuration or memory-map type of access.
5.16.2.7
Position
7:0
Register Offset.
Description
Data Field
This field is used to receive read data or to provide write data associated with the
addressed register.
At the completion of a read command, this field will contain the data retrieved from the
addressed register. All reads will return an entire aligned DWord (32 bits) of data.
For write operations, the number of byte(s) of this 32 bit field is loaded with the desired
write data. For a byte write only bits 7:0 will be used, for a Word write only bits 15:0
will be used, and for a DWord write all 32 bits will be used.
Position
31:24
23:16
15:8
7:0
Description
Byte 3 (DATA3). Data bits [31:24] for DWord.
Byte 2 (DATA2). Data bits [23:16] for DWord.
Byte 1 (DATA1). Data bits [15:8] for DWord and Word.
Byte 0 (DATA0). Data bits [7:0] for DWord, Word and Byte.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet