QG5000XSL9TH Datasheet, PDF (136/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.10.4
MSIAR[7:2, 0] - MSI Address Register
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts and is broken into its constituent fields.
3.8.10.5
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
5Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
5Ch
Intel 5000Z Chipset
4-7
0
5Ch
Intel 5000P Chipset
Bit
31:20
Attr
RO
19:12 RW
11:4 RW
3
RW
2
RW
1:0
RV
Default
FEEh
00h
00h
0h
0h
0h
Description
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
AEXDSTID: Address Extended Destination ID
This field is not used by IA32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
ADM: Address Destination Mode
0: physical
1: logical
Reserved.
Not used since the memory write is D-word aligned
MSIDR[7:2, 0] - MSI Data Register
The MSI Data Register (MSIDR) contains all the data (interrupt vector) related
information to route MSI interrupts.
136
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet