QG5000XSL9TH Datasheet, PDF (245/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 21
Function: 0
Offset: 28Ch, 18Ch
Bit Attr
Default
13:10 RWST
0h
9:0 RWST
3FFh
Description
txmaskhvm: Transmit Mask extra DFT pins for HVM symmetry
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
txmask: Transmit Mask
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
3.9.25.9
FBD[3:2]IBRXMSK: Intel IBIST Receiver Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device: 22
Function: 0
Offset: 290h, 190h
Bit
31:14
Attr
RV
13:0 RWST
Default
0h
1FFFh
Description
Reserved
rxmask: Receive Mask
Selects which lanes to enable for testing. An Rx lane that is not selected is not
included in Rx channel training does not contribute to the accumulation of
error counts.
3.9.25.10 FBD[1:0]IBRXMSK: Intel IBIST Receiver Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device: 21
Function: 0
Offset: 290h, 190h
Bit
31:14
Attr
RV
13:0 RWST
Default
0h
1FFFh
Description
Reserved
rxmask: Receive Mask
Selects which lanes to enable for testing. An Rx lane that is not selected is not
included in Rx channel training does not contribute to the accumulation of
error counts.
3.9.25.11 FBD[3:2]IBTXSHFT: Intel IBIST Transmit Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device: 22
Function: 0
Offset: 294h, 194h
Bit
31:14
Attr
RV
Default
0h
Reserved
Description
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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