QG5000XSL9TH Datasheet, PDF (400/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Figure 6-5. TAP Instruction Register Access
Testability
6.1.7
6.1.8
Accessing the Data Registers
The test data registers in the Intel 5000P chipset components are architected in the
same way as the instruction register, with components (that is, either the “capture” or
“update” functionality) removed from the basic structure as needed. Data registers are
accessed just as the instruction register is, only using the “select-DR-scan” branch of
the TAP finite state machine in Table 6-2. A specific data register is selected for access
by each TAP instruction. Note that the only controller states in which data register
contents actually change are Capture-DR, Shift-DR, Update-DR and Run-Test/ Idle. For
each of the TAP instructions described below, therefore, it is noted what operation (if
any) occurs in the selected data register in each of these four states.
Public TAP Instructions
Table 6-3 contains descriptions of the encoding and operation of the public TAP
instructions. There are four 1149.1-defined instructions implemented in the Intel
5000P Chipset devices. These instructions select from among three different TAP data
registers – the boundary scan, device ID, and bypass registers. The public instructions
can be executed with only the standard connection of the JTAG port pins. This means
the only clock required will be TCK. Full details of the operation of these instructions
can be found in the 1149.1 standard. The opcodes are 1149.1-compliant, and are
consistent with the Intel-standard encodings. A brief description of each instruction
follows. For more thorough descriptions refer to the IEEE 1149.1 specification.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet