QG5000XSL9TH Datasheet, PDF (133/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
54h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
54h
Intel 5000Z Chipset
4-7
0
54h
Intel 5000P Chipset
Bit
31:24
Attr
RO
23
RO
22
RO
21:16
15
RV
RWCST
14:13
RO
12:9
RO
8
RWST
7:2
RV
1:0
RW
Default
00h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Description
Data: Data
Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI PM
specification for details. This is not implemented in the Power Management
capability for Intel 5000P Chipset MCH and is hardwired to 0h.
BPCCEN: Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
B2B3S: B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
Reserved.
PMESTS: PME Status
This PME Status is a sticky bit. When set, the PCI Express port generates a
PME internally independent of the PMEEN bit defined below. Software
clears this bit by writing a ‘1’ when it has been completed.
As a root port, the Intel 5000P Chipset MCH will never set this bit, because
it never generates a PME internally independent of the PMEEN bit.
DSCL: Data Scale
This 2-bit field indicates the scaling factor to be used while interpreting the
“data_scale” field.
DSEL: Data Select
This 4-bit field is used to select which data is to reported through the “data”
and the “Data Scale” fields.
PMEEN: PME Enable
This field is a sticky bit and when set enables PMEs generated internally to
appear at the Intel 631xESB/632xESB I/O Controller Hub through the
“Assert(Deassert)_PMEGPE”message. This has no effect on the Intel 5000P
Chipset MCH since it does not generate PME events internally.
Reserved.
PS: Power State
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (reserved)
10: D2 (reserved)
11: D3_hot
If Software sets this to D1 or D2, then the power state will default to D0.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
133