QG5000XSL9TH Datasheet, PDF (244/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.25.5
3.9.25.6
3.9.25.7
3.9.25.8
FBD[3:2]IBPATBUF: FB-DIMM Intel BIST Pattern Buffer Register
This register contains the pattern bits used in Intel IBIST operations.
Device: 22
Function: 0
Offset: 288h, 188h
Bit Attr
Default
31:24 RV
0
23:0 RWST 02CCFDh
Description
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
FBD[1:0]IBPATBUF: FB-DIMM Intel IBIST Pattern Buffer Register
This register contains the pattern bits used in Intel IBIST operations.
Device: 21
Function: 0
Offset: 288h, 188h
Bit Attr
Default
31:24 RV
0
23:0 RWST 02CCFDh
Description
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
FBD[3:2]IBTXMSK: Intel IBIST Transmitter Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device: 22
Function: 0
Offset: 28Ch, 18Ch
Bit
31:14
Attr
RV
13:10 RWST
9:0 RWST
Default
0h
0h
3FFh
Description
Reserved
txmaskhvm: Transmit Mask extra DFT pins for HVM symmetry
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
txmask: Transmit Mask
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
FBD[1:0]IBTXMSK: Intel IBIST Transmitter Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device: 21
Function: 0
Offset: 28Ch, 18Ch
Bit
31:14
Attr
RV
Default
0h
Reserved
Description
244
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet