QG5000XSL9TH Datasheet, PDF (300/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.1.2
FSB Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data
from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the MCH. The DBI[3:0]# signals indicate if the corresponding 16 bits of
data are inverted on the bus for each quad pumped data phase.
Table 5-1.
DBI[3:0]# / Data Bit Correspondence
DBI[3:0]#
DBI0#
DBI1#
DBI2#
DBI3#
Data Bits
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more
than 8 of the 16 signals would normally be driven low on the bus, the corresponding
DBI# signal will be asserted and the data will be inverted prior to being driven on the
bus. When the processor or the MCH receives data, it monitors DBI[3:0]# to determine
if the corresponding data segment should be inverted.
5.1.3
FSB Interrupt Overview
The Dual-Core Intel Xeon 5000 Sequence processor supports FSB interrupt delivery.
The legacy APIC serial bus interrupt delivery mechanism is not supported. Interrupt-
related messages are encoded on the FSB as “Interrupt Message Transactions.” In the
Intel 5000X chipset platform, FSB interrupts may originate from the processor on the
system bus, or from a downstream device on the Enterprise South Bridge Interface
(ESI) or AGP. In the later case, the MCH drives the Interrupt Message Transaction onto
the system bus.
In the Intel 5000X chipset the Intel 631xESB/632xESB I/O Controller Hub contains
IOxAPICs, and its interrupts are generated as upstream ESI memory writes.
Furthermore, PCI 2.3 defines Message Signaled Interrupts (MSI) that are also in the
form of memory writes. A PCI 2.3 device may generate an interrupt as an MSI cycle on
its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be
directed to the IOxAPIC which in turn generates an interrupt as an upstream ESI
memory write. Alternatively, the MSI may be directed directly to the FSB. The target of
an MSI is dependent on the address of the interrupt memory write. The MCH forwards
inbound ESI and AGP/PCI (PCI semantic only) memory writes to address 0FEEx_xxxxh
to the FSB as Interrupt Message Transactions.
5.1.3.1
Upstream Interrupt Messages
The MCH accepts message-based interrupts from PCI (PCI semantics only) or ESI and
forwards them to the FSB as Interrupt Message Transactions. The interrupt messages
presented to the MCH are in the form of memory writes to address 0FEEx xxxxh. At the
ESI or PCI interface, the memory write interrupt message is treated like any other
memory write; it is either posted into the inbound data buffer (if space is available) or
retried (if data buffer space is not immediately available). Once posted, the memory
write from PCI or ESI to address 0FEEx xxxxh is decoded as a cycle that needs to be
propagated by the MCH to the FSB as an Interrupt Message Transaction.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet