QG5000XSL9TH Datasheet, PDF (329/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Table 5-9. FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling
THRMTHRT
Reg Value Activates
0 unlimited
1
4
2
8
3
12
4
16
5
20
6
24
7
28
8
32
12
48
16
64
20
80
24
96
28
112
32
128
36
144
40
160
44
176
48
192
64
256
72
288
80
320
96
384
128
512
144
576
160
640
168
672
% BW
allowed
BW per sys BW, 1 sys BW 2 sys BW 4
DIMM GB/s DIMM/ch DIMM/ch DIMM/ch
0.60%
1.19%
1.79%
2.38%
2.98%
3.57%
4.17%
4.76%
7.14%
9.52%
11.90%
14.29%
16.67%
19.05%
21.43%
23.81%
26.19%
28.57%
38.10%
42.86%
47.62%
57.14%
76.19%
85.71%
95.24%
100.00%
0.03
0.13
0.25
0.51
0.06
0.25
0.51
1.02
0.10
0.38
0.76
1.52
0.13
0.51
1.02
2.03
0.16
0.63
1.27
2.54
0.19
0.76
1.52
3.05
0.22
0.89
1.78
3.56
0.25
1.02
2.03
4.06
0.38
1.52
3.05
6.10
0.51
2.03
4.06
8.13
0.63
2.54
5.08
10.16
0.76
3.05
6.10
12.19
0.89
3.56
7.11
14.22
1.02
4.06
8.13
16.25
1.14
4.57
9.14
18.29
1.27
5.08
10.16
20.32
1.40
5.59
11.17
1.52
6.10
12.19
2.03
8.13
16.25
2.29
9.14
18.29
2.54
10.16
20.32
3.05
12.19
4.06
16.25
4.57
18.29
5.08
20.32
5.33
21.33
5.3.12.7
Open Loop Global Throttling
In the open loop global window throttling scheme, the number of activates per DIMM
pair per branch is counted for a larger time period called the “Global Throttling
window”. The Global throttling window is chosen as an integral multiple of the thermal
throttling window of 1344 clocks for maintaining a simpler implementation. Under
normal operating conditions, the Global Throttling Window is 0.65625*2²⁵clocks in
duration and this translates to 16384*1344 clocks (~66.06 ms) for DDR2667. However,
for purposes of validation and debug, the global throttling window can be reduced to a
smaller duration, 4*1344 cycles¹ (16.128 μs) for DDR2667 and this is controlled
through the GTW_MODE register bit defined in Section 3.9.1. The global throttling
window prevents shorts peaks in bandwidth from causing closed loop activation
throttling when there has not been sufficient DRAM activity over a long period of time
to warrant throttling. It is in effect a low pass filter on the closed loop activation
throttling.
1. If MC.GTW_MODE=1, the Intel 5000X chipset MCH will use the 4*1344 cycle duration for the
global throttling window.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
329