QG5000XSL9TH Datasheet, PDF (309/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-4. Single DIMM Operation Mode
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
BRANCH 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 2
CHANNEL 3
BRANCH 1
Memory Controller
5.3.1.2
Mirrored Mode Memory Upgrades
When operating in mirrored mode both branches operate in lock step. In mirrored
mode Branch 1 contains a replicate copy of the data in Branch 0. For this reason the
minimum memory upgrade increment, for mirrored mode, is four DIMMs across all
branches. The DIMMs must cover the same slot position on both branches. DIMMs that
cover a slot position must be identical with respect to size, speed, and organization.
DIMMs within a slot position must match each other, but aren’t required to match
adjacent slot positions.
Figure 5-5 shows the minimum memory configuration required to operate in mirrored
mode.
Figure 5-5. Minimum Mirrored Mode Memory Configuration
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
BRANCH 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 2
CHANNEL 3
BRANCH 1
Memory Controller
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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