QG5000XSL9TH Datasheet, PDF (260/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.10.9 MSICAPID - Message Signalled Interrupt Capability ID
Register
Device:
Function:
Offset:
Version:
8
0
58h
Intel 5000P Chipset
Bit
7:0
Attr Default
Description
RO
05h
CAPID: MSI Capability ID
This code denotes the standard MSI capability assigned by PCI-SIG
3.10.10 MSINXPTR - Message Signalled Interrupt Next Pointer
Register
Device:
Function:
Offset:
Version:
8
0
59h
Intel 5000P Chipset
Bit
7:0
Attr Default
Description
RO
6Ch
NXTPTR: MSI Next Pointer: The DMA Engine device is implemented as a PCI
Express device and this points to the PCI Express capability structure.
3.10.11 MSICTRL - Message Signalled Interrupt Control Register
Device:
Function:
Offset:
Version:
8
0
5Ah
Intel 5000P Chipset
Bit
15:8
7
6:4
3:1
0
Attr Default
Description
RO
0h
RO
0
RW
000
RO
0h
Reserved
AD64CAP: 64-bit Address Capable
All processors used with the GNC MCH do not support 64-bit addressing, hence this
is hardwired to 0
MMEN: Multiple Message Enable
Software initializes this to indicate the number of allocate messages which is
aligned to a power of two. When MSI is enabled, the software will allocate at least
one message to the device. See Section 3.10.13 below for discussion on how the
interrupts are handled.
MMCAP: Multiple Message Capable
The Intel 5000P Chipset MCH DMA Engine supports only one interrupt message
(power of two) for handling
• DMA errors
• DMA completions
RW
0
MSIEN: MSI Enable
This bit enables MSI as the interrupt mode of operation instead of the legacy
interrupt mechanism.
0: Disables MSI from being generated.
1: Enables MSI messages to be generated for DMA related interrupts.
An extract of the flowchart of the DMA Engine error handling is given in Figure 3-7
260
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet