QG5000XSL9TH Datasheet, PDF (306/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
The four FB-DIMM channels are organized into two branches of two channels per
branch. Each branch is supported by a separate Memory Controller (MC). The two
channels on each branch operate in lock step to increase FB-DIMM bandwidth. A branch
transfers 16 bytes of payload/frame on Southbound lanes and 32 bytes of payload/
frame on Northbound lanes.
The two branches may be operated in mirrored (RAID 1) or non-mirrored mode. When
operating in mirrored mode, 64 GB of memory will produce an effective 32 GB memory
space.
The key features of the FB-DIMM memory interface are summarized in the following
list.
• Four Fully Buffered DDR (FB-DIMM) memory channels.
• Branch channels are paired together in lock step to match FSB bandwidth
requirement.
• Each FB-DIMM Channel can link up to four Fully Buffered - DDR DIMMs (FB-DIMM).
• Supports up to 16 dual-ranked FB-DDR2 4GB DIMMs, that is, 64GB¹of physical
memory in non-mirrored configuration or 32GB of physical memory in mirrored
configuration.
• The FB-DIMM link speed is at 6x the DDR data transfer speed. A 3.2 GHz FB-DIMM
link supports DDR2-533 (FSB@1067 MT/s).
• The MCH will comply with the FB-DIMM specification definition of a host and will be
compatible with any FB-DIMM-compliant DIMM.
• Special single channel, single DIMM operation mode (Branch 0, Channel 0, Slot 0
position only).
• All memory devices must be DDR2.
Table 5-2 and Figure 5-4 present system memory capacity as a function of DRAM
device capacity and MCH operating mode.
Table 5-2.
Minimum System Memory Configurations & Upgrade Increments
DRAM Technology
256 Mb
512 Mb
1024 Mb
2048 Mb
Smallest System
Configuration - One
DIMM
256 MB
512 MB
1024 MB
2048 MB
Smallest Upgrade
Increment - Two
DIMM
512 MB
1024 MB
2048 MB
4096 MB
The Smallest System Configuration - One DIMM column represents the smallest
possible single DIMM capacity for a given technology (MCH operating in single channel,
single DIMM mode with x8 single rank (x8SR) DIMM populated). The Smallest Upgrade
Increment - Two DIMMs column represents the smallest possible memory upgrade
capacity for a given technology using two x8 single rank DIMMs.
1. User can only access up to 63.5 GB of memory due to minimum 256 MB MMIO/TOLM and limited
address decoding above 64 GB.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet