QG5000XSL9TH Datasheet, PDF (167/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.12.9
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
110h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
110h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
110h
Intel 5000P Chipset
Bit
Attr
Default
Description
7
RWCST
6
RWCST
5:1
RV
0
RWCST
0
IO14Err: Bad DLLP Status
0
IO13Err: Bad TLP Status
0h
Reserved
0
IO12Err: Receiver Error Status
CORERRMSK[7:2, 0] - Correctable Error Mask
This register masks correctable errors from being signalled. They are still logged in the
CORERRSTS register.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
114h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
114h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
114h
Intel 5000P Chipset
Bit
31:13
12
11:9
8
7
6
5:1
0
Attr
RV
RWST
RV
RWST
RWST
RWST
RV
RWST
Default
0h
0
0h
0
0
0
0h
0
Description
Reserved
IO16Msk: Replay Timer Time-out Mask
Reserved
IO15Msk: Replay_Num Rollover Mask
IO14Msk: Bad DLLP Mask
IO13Msk: Bad TLP Mask
Reserved
IO12Msk: Receiver Error Mask
3.8.12.10 AERRCAPCTRL[7:2, 0] - Advanced Error Capabilities and Control
Register
This register identifies the capability structure and points to the next structure.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
167