QG5000XSL9TH Datasheet, PDF (410/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Electrical Characteristics
7.2.4 PCI Express/ ESI Interface DC Characteristics
Table 7-8. PCI Express/ ESI Differential Transmitter (Tx) Output DC Characteristics
Symbol
VTX-DIF-DC
VTX-CM-DC-
ACTIVE-
IDLE-DELTA
VTX-CM-DC-
LINE-DELTA
VTX-IDLE-
DIFFp
VTX-RCV-
DETECT
VTX-DC-CM
ITX-SHORT
ZTX-DIFF-DC
ZTX-DC
Signal
Group
(o) (p)
(o) (p)
(o) (p)
(o) (p)
(o) (p)
(o) (p)
(o) (p)
(o) (p)
(o) (p)
Parameter
Differential Peak to Peak
Output Voltage
Absolute Delta of DC
Common Mode Voltage
During L0 and Electrical
Idle
Absolute Delta of DC
Common Mode Voltage
between D+ and D-
Electrical Idle Differential
Peak Output Voltage
The amount of voltage
change allowed during
Receiver Detection
The TX DC Common Mode
Voltage
The Short Circuit Current
Limit
DC Differential TX
Impedance
Transmitter DC Impedance
Min
0.8
0
0
0
80
40
Nom
100
Max
1.2
100
25
20
600
3.6
90
120
Unit
V
Note
s
2
mV
2
mV
2
mV
2
mV
V
2
mA
Ω
Ω
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive
TX UIs.
Table 7-9. PCI Express/ ESI Differential Receiver (Rx) Input DC Characteristics
Symbol
ZRX-DIFF-DC
ZRX-DC
ZRX-High-
Imp-DC
VRX-IDLE-
DET-DIFFp
Signal
Group
(o) (p)
(o) (p)
(o) (p)
(o) (p)
Parameter
DC Differential Input
Impedance
DC Input Impedance
Power Down DC Input
Common Mode Impedance
Electrical Idle Detect
Threshold
Min
80
40
200k
65
Nom
100
50
Max
120
60
175
Unit
Ω
Note
s
5
Ω
2, 3
Ω
6
mV
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. If the clock to the RX and TX are not
derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the
eye diagram.
3. A TRX-EYE=0.40UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total.6 UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured
by a Vector Network Analyzer with 50 ohm probes). Note: that the series capacitors CTX is optional for the return loss
measurement.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet