QG5000XSL9TH Datasheet, PDF (104/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
0, 2-3
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
4-5
Function: 0
Offset:
04h
Version: Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
04h
Intel 5000P Chipset
Bit
Attr
Default
Description
2
RW
1
if (port
7-2)
{RW}
elseif
(port 0)
{RO}
endif
0
if (port
7-2)
{RW}
elseif
(port 0)
{RO}
endif
0
BME: Bus Master Enable
Controls the ability of the PCI Express port to forward memory or I/O
transactions.
1: Enables the PCI Express port to successfully complete the memory or I/
O read/write requests.
0: The Bus Master is disabled. The MCH will treat upstream memory writes/
reads, I/O writes/reads, and MSIs as illegal cycles and return Unsupported
Request Status (equivalent to Master abort) in PCI Express
When the BME is disabled, the MCH will treat upstream memory writes/
reads, I/O writes/reads, and MSIs as illegal cycles and return Unsupported
Request Status (equivalent to Master abort) in PCI Express
Requests other than inbound memory or I/O (for example, configuration,
outbound) are not controlled by this bit.
The BME is typically used by the system software for operations such as
hot-plug, device configuration.
When the CPURESET# signal is asserted during a power good or hard reset
and after the DMI completes its training, the LPC device in the Intel
631xESB/632xESB I/O Controller Hub (or other NIC/SIO4 cards could
potentially send inbound requests even before the CPURESET# is
deassserted. This corner case is handled by the BME filtration in the Intel
5000P Chipset MCH’s PCI Express port using the above rules since BME is
reset. However, in general, it is illegal for a an I/O device to issue inbound
requests until the CPURESET# has been deasserted to prevent any possible
malfunction in the Intel 5000P Chipset MCH logic.
0
MSE: Memory Space Enable
Controls the bridge’s response as a target to memory accesses on the
primary interface that address a device that resides behind the bridge in
both the non-prefetchable and prefetchable memory ranges (high/low) or
targets a memory-mapped location within the bridge itself
1: Enables the Memory and Prefetchable memory address ranges (MMIO)
defined in the MBASE/MLIM, PMBASE/PMLIM, PMBU/PMLU registers.
0: Disables the entire memory space seen by the PCI Express port on the
primary side (MCH). Requests will then be subtractively claimed by Intel
631xESB/632xESB I/O Controller Hub. For port 0, this bit is hardwired to 0
since the ESI is not a P2P bridge.
0
IOAE: Access Enable
1: Enables the I/O address range defined in the IOBASE and IOLIM
registers.
0: Disables the entire I/O space seen by the PCI Express port on the
primary. Requests will be then be subtractively claimed by Intel 631xESB/
632xESB I/O Controller Hub.
For port 0, this bit is hardwired to 0 since the ESI is not a P2P bridge.
Notes:
1. In addition, BCCTRL.BCSERRE also gates the transmission of ERR_FATAL, NON_FATAL and ERR_COR messages
received from the PCI Express interface. See Section 3.8.8.28.
104
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet