QG5000XSL9TH Datasheet, PDF (3/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Contents
1 Introduction ............................................................................................................ 13
1.1 Terminology ..................................................................................................... 13
1.2 Related Documents ........................................................................................... 19
1.3 Intel® 5000X Chipset Overview .......................................................................... 19
2 Signal Description ................................................................................................... 23
2.1 Processor Front Side Bus Signals ......................................................................... 25
2.1.1 Processor Front Side Bus 0 ...................................................................... 25
2.1.2 Processor Front Side Bus 1 ...................................................................... 27
2.2 Fully Buffered DIMM Memory Channels................................................................. 29
2.2.1 FB-DIMM Branch 0 ................................................................................. 29
2.2.2 FB-DIMM Branch 1 ................................................................................. 30
2.3 PCI Express* Signal List ..................................................................................... 30
2.3.1 PCI Express* Common Signals ................................................................. 30
2.3.2 PCI Express Port 0, Enterprise South Bridge Interface (ESI) ......................... 31
2.3.3 PCI Express Port 2.................................................................................. 31
2.3.4 PCI Express Port 3.................................................................................. 31
2.3.5 PCI Express* Graphics Port...................................................................... 32
2.4 System Management Bus Interfaces .................................................................... 33
2.5 XD Port Signal List............................................................................................. 33
2.6 JTAG Bus Signal List .......................................................................................... 33
2.7 Clocks, Reset and Miscellaneous .......................................................................... 34
2.8 Power and Ground Signals .................................................................................. 34
2.9 MCH Sequencing Requirements ........................................................................... 34
2.10 Reset Requirements........................................................................................... 36
2.10.1 Timing Diagrams .................................................................................... 36
2.10.2 Reset Timing Requirements ..................................................................... 38
2.10.3 Miscellaneous Requirements and Limitations .............................................. 39
2.11 Intel® 5000P Chipset Platform Signal Routing Topology Diagrams ........................... 40
2.11.1 Intel® 5000P Customer Reference Platform (SRP) Reset Topology ................ 41
2.12 Signals Used as Straps....................................................................................... 41
2.12.1 Functional Straps ................................................................................... 41
3 Register Description ................................................................................................ 43
3.1 Register Terminology ......................................................................................... 43
3.2 Platform Configuration Structure ......................................................................... 44
3.3 Routing Configuration Accesses ........................................................................... 47
3.3.1 Standard PCI Bus Configuration Mechanism ............................................... 47
3.3.2 PCI Bus 0 Configuration Mechanism .......................................................... 47
3.3.3 Primary PCI and Downstream Configuration Mechanism............................... 48
3.4 Device Mapping................................................................................................. 48
3.4.1 Device Identification for Intel 5000P Chipset, Intel 5000Z Chipset,
and Intel 5000V Chipset Components........................................................ 49
3.4.2 Special Device and Function Routing ......................................................... 50
3.5 I/O Mapped Registers ........................................................................................ 51
3.5.1 CFGADR: Configuration Address Register................................................... 51
3.5.2 CFGDAT: Configuration Data Register ....................................................... 52
3.6 MCH Fixed Memory Mapped Registers .................................................................. 52
3.7 Detailed Configuration Space Maps ...................................................................... 53
3.8 Register Definitions ........................................................................................... 72
3.8.1 PCI Standard Registers ........................................................................... 72
3.8.2 Address Mapping Registers ...................................................................... 81
3.8.3 AMB Memory Mapped Registers................................................................ 90
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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