QG5000XSL9TH Datasheet, PDF (124/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 0
Function: 0
Offset: 40h
Bit
3:1
0
Attr Default
Description
RWST 000
RWST 0
GPMNXT0: IOU0 max width Configuration Next (ports 2-3)
The IOU0 cluster will use this field to train the links after a hard reset provided
LWOEN is set.
Refer to Table 3.8.8.30, “PEXCTRL[7,2:0]: PCI EXPRESS Control Register” on
page 126
LWOEN: Link Width override Enable
0: Disables software from setting the PCI Express link width through this register
and the Link width is controlled by the external pins PEWIDTH[3:0]. (default).
1. Enables BIOS/Software to set the required link width through this register. When
this bit is set, the IOU cluster will ignore the external pin strap (PEWIDTH[3:0] and
use the described table for configuring the link width. The values will take effect
after a hard reset.
124
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet