QG5000XSL9TH Datasheet, PDF (333/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.3.13
Electrical Throttling
Electrical throttling is a mechanism that limits the number of activates (burstiness)
within a very short time interval that would otherwise cause silent data corruption on
the DIMMs. Electrical throttling is enabled by setting the MTR.ETHROTTLE bit defined in
Section 3.9.23.7. These bits occur on a per DIMM pair basis per branch as to whether
electrical throttling should be used. It is assumed that both ranks within a DIMM would
be the same technology, and therefore does need not separate enable bits.
The per rank electrical throttling for FB-DIMM is 4 activates per 37.5ns window (JEDEC
consensus) and is summarized in Table 5-11 for various DIMM technologies.
Table 5-11. Electrical Throttle Window as a Function of DIMM Technology
DIMM Modes
Intel 5000P
Chipset MCH
Core: FB-DIMM
clock Ratio
Electrical Throttle Window¹ (in core clocks per rank
per DIMM pair per branch)
DDR533
1:1
10
5:4
13
DDR667
1:1
13
4:5
DDR800^b
All
13 (conservative)
15
Conservative
All
20
(safe mode)
Notes:
1. Maximum 4 activates per rank is allowed within the window.
b. This is not a supported technology/nor a POR for Intel 5000P Chipset MCH and is tabulated for
information/illustrative purposes only.
The MC.ETHROT configuration register field limits the number of activations per sliding
electrical throttle window. The memory controller logic can implement the sliding
electrical throttle window with a 20-bit shift register per rank in each DIMM pair per
branch. This register records for the last 20 clocks, whether an activate was issued or
not to that rank. The number of activates can then be summed up from the state of the
shift register and compared with the respective limit as shown in Figure 5-11. If the
limit is reached, then further activates to the rank are blocked until the count falls
below the limit. The Electrical throttling logic in the MC masks off the end bits for the
DIMM technologies that require fewer clocks. As an example, if the DIMM technology
used is DDR667, then it can allow 4 activates within the last 13 clocks, the remaining 7
bits are masked (forced to 0) so they do not prevent activates.
5.4
Note:
Behavior on Overtemp State in AMB
Overtemperature occurring in an AMB may lead to data corruption in the .
• If EI is received by due to Overtemp detection in one of the AMBs, will capture
random data that most likely will be interpreted as having a CRC or uncorrectable
ECC error causing the link to go into a fast reset loop without data corruption.
• If the EI is interpreted as having both good CRC and good ECC, this could cause
data corruption until a bad CRC/ECC frame is detected and the link enters the fast
reset loop.
An all 0 frame fits this case of good CRC and ECC. This is just as unlikely as any other
random frame contents when interpreting EI.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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