QG5000XSL9TH Datasheet, PDF (266/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
8
0
74h
Intel 5000P Chipset
Bit
3
2
1
0
Attr Default
Description
RO
0
RW
0
RW
0
RW
0
URREN: Unsupported Request Reporting Enable
For an integrated DMA Engine device, this bit is irrelevant. Hardwired to 0h
FERE: Fatal Error Reporting Enable:
This bit controls the reporting of fatal errors internal to the DMA Engine device
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
NFERE: Non-Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the DMA Engine device
in the PCI Express port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
This has no effect on the Intel 5000P Chipset MCH DMA Engine device as it does not
report any non-fatal errors.
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the DMA Engine
device in the PCI Express port.
0: Correctable error reporting is disabled
1: Correctable Fatal error reporting is enabled
This has no effect on the Intel 5000P Chipset MCH DMA Engine device as it does not
report any correctable errors.
3.10.19 PEXDEVSTS - PCI Express Device Status Register
Device:
Function:
Offset:
Version:
8
0
76h
Intel 5000P Chipset
Bit
15:6
5
4
3
2
Attr Default
Description
RV
0h
RO
0
RO
0
RO
0
RWC 0
Reserved
TP: Transactions Pending
This bit indicates that the DMA Engine device has issued non-posted PCI Express
transactions which have not yet completed.
Note the Intel 5000P Chipset MCH DMA Engine device does not issue any NP
transactions and hence this is hardwired to zero.
APD: AUX Power Detected
The DMA Engine device does not support AUX power. Hardwired to 0h.
URD: Unsupported Request Detected
This does not apply to DMA Engine in Intel 5000 Series Chipset as there are no
messages for the DMA engine. Hardwired to 0h
FED: Fatal Error Detected
This bit gets set if a fatal uncorrectable error is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device Control
register (See FERE in Section 3.10.18)
1: Fatal errors detected
0: No Fatal errors detected
266
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet