QG5000XSL9TH Datasheet, PDF (108/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.6
3.8.8.7
3.8.8.8
3.8.8.9
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 3-2
0
0Fh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
0Fh
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
7-4
0
0Fh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
BIST_TST: BIST Tests
Not supported. Hardwired to 00h
BAR0[7:2,0] - Base Address Register 0
Base address registers are used for mapping internal registers to an MMIO or I/O
space. It does not affect the MCH. The base address register 0 is not supported/defined
in the PCI Express port of the MCH.
BAR1[7:2,0] - Base Address Register 1
The base address register 1 is not supported/defined in the MCH.
EXP_ROM[0]: Expansion ROM Registers
The ESI port (device 0, function 0) does not implement any Base address registers in
the Intel 5000P Chipset MCH from offset 10h to 24h. Similarly no Expansion ROM base
address register is defined in offset 30h. Also no Cardbus CIS pointer is defined in
offset 28h. The MIN_GNT (offset 3Eh) and MAX_LAT (3Fh) registers are also not
implemented as they are not applicable to the ESI interface.
PBUSN[7:2] - Primary Bus Number
This register identifies the bus number on the on the primary side (MCH) of the PCI
Express port.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet