QG5000XSL9TH Datasheet, PDF (296/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Figure 4-4. System I/O Address Space
1_0003
FFFF
+3 bytes
(Decoded
as 0_000X)
Segment 15
Segment F
F000
System Address Map
2000
Segment 1
1000
Segment 0
4.5.2.1
0000
Outbound I/O Accesses Routing
The Intel 5000P Chipset applies these routing rules in the following order:
(A[2:0] for the following is not physically present on the processor bus, but are
calculated from BE[7:0]).
1. I/O addresses used for VGA controllers on PCI Express:
If PCICMD[y].IOAE and BCTRL[y].VGAEN of PCI Express port y are set to 1 and
BCTRL[y].VGA16bdecode = 0, then I/O accesses with the following VGA addresses
will be forwarded to PCI Express port y: A[9:0] (A[15:10] are ignored for this
decode since BCTRL[y].VGA16bdecode is set to 0) = 3B0h - 3BBh, 3C0h - 3DFh if
every addressed byte is within these two ranges. For example, a two byte read
starting at X3BBh includes X3BB -X3BCh. (X can be any hex number since
A[15:10] are ignored) Since the second byte with A[9:0] = 3BCh is not within
these ranges, the access is not routed to port y.
If PCICMD[y].IOAE and BCTRL[y].VGAEN of port y are set to 1 and
BCTRL[y].VGA16bdecode = 1, then I/O accesses with the following VGA addresses
will be forwarded to PCI Express port y: A[15:0] = 03B0h - 03BBh, 03C0h - 03DFh
if every addressed byte is within these two ranges. For example, a four byte I/O
read starting at F3B0h includes F3B0 - F3B3h are not within these ranges, the
access is not routed to port y.
Note that software should program PEXCMDs and BCTRLs to ensure that at most
only one port is allowed to forward these accesses with VGA addresses. It is a
programming error if more than one port are programmed to forward accesses with
VGA addresses.
2. Configuration accesses: If a request is a DW accesses to 0CF8h (See CFGADR
register) or
1-4 B accesses to 0CFCh (See CFGDAT register) with configuration space enabled
(See CFGE bit, bit 31, of CFGADR register), the request is considered a
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet