QG5000XSL9TH Datasheet, PDF (159/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11.13 PEXRTSTS[7:2, 0] - PCI Express Root Status Register
The PCI Express Root Status register specifies parameters specific to the root
complex port.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
8Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
8Ch
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
8Ch
Intel 5000P Chipset
Bit
Attr
Default
Description
31:18 RV
17
RO
16
RWC
15:0 RO
0h
0h
0h
0000h
Reserved.
PMEPEND: PME Pending
This field indicates that another PME is pending when the PME Status bit is
set. When the PME Status bit is cleared by software; the pending PME is
delivered by hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by hardware if no
more PMEs are pending.
Note:
The Intel 5000P Chipset MCH can handle two outstanding PM_PME
messages in its internal queues of the Power Management controller
per port. If the downstream device issues more than 2 PM_PME
messages successively, it will be dropped.
PMESTATUS: PME Status¹
This field indicates status of a PME that is underway in the PCI Express port.
1: PME was asserted by a requester as indicated by the PMEREQID field
This bit is cleared by software by writing a ‘1’. Subsequent PMEs are kept
pending until the PME Status is cleared.
PMEREQID: PME Requester ID
This field indicates the PCI requester ID of the last PME requestor.
Notes:
1. PMEINTEN defined in PEXRTCTRL has to be set for PM interrupts to be generated. For non-MSI PM
interrupts, the PMESTATUS bit in each of the PEXRTSTS[2:7] registers are wired OR together and when set,
the MCH will send the “Assert_PMEGPE” message to the Intel 631xESB/632xESB I/O Controller Hub for
power management. When all the bits are clear, it will send the “Deassert_PMEGPE” message. PMEINTEN
defined in PEXRTCTRL has to be set for PM interrupts to be generated. PM_PME events that generate MSI
will depend on the MSIEN field in Section 3.8.10.3. Refer to the PM interrupt flow in Power Management
Chapter.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
159