QG5000XSL9TH Datasheet, PDF (291/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
Table 4-6.
Address Disposition for Processor (Sheet 2 of 2)
Address
Range
Conditions
Intel 5000P Chipset Behavior
E and F BIOS
segments
0E0000h to 0FFFFFh and PAM=11
Write to
0E0000h to 0FFFFFh and PAM=10
Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Chipset MCH.MIR registers.
Read to
0E0000h to 0FFFFFh and PAM=01
Read to
Issue request to ESI.
0E0000h to 0FFFFFh and PAM=10
Write to
0E0000h to 0FFFFFh and PAM=01
0E0000h to 0FFFFFh and PAM=00
Low/Medium
Memory
10_0000 <= Addr < TOLM
Coherent request to main memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Coherence protocol is applied.
Note: The extended SMRAM space is within this range.
Extended
ESMMTOP-TSEG_SZ <= Addr <
SMRAM Space ESMMTOP
see Table 4-8 and Table 4-9.
Low MMIO
TOLM <= Addr < FE00_0000 and Request to PCI Express based on <MBASE/MLIMIT and
falls into a legal BASE/LIMIT range PMBASE/PMLIMIT> registers.
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
Send to ESI to be master aborted.
PCI Express
MMCFG
HECBASE <= Addr <
HECBASE+256MB
Convert to a configuration access and route according
to the Configuration Access Disposition.
Intel 5000X
chipset specific
FE00_0000h to FEBF_FFFFh AND
valid Intel 5000P Chipset memory
mapped register address plus AMB
targeted addresses
Issue configuration access to memory mapped register
inside Intel 5000P Chipset or to the FB-DIMM based on
the context.
FE00_0000h to FEBF_FFFFh AND
(NOT a valid Intel 5000P Chipset
memory mapped register address
or NOT a valid AMB targeted
address)
Send to ESI to be master aborted.
I/O APIC
registers
FEC0_0000 to FEC8_FFFFh
Non-coherent request to PCI Express or ESI based on
Table 4-4.
Intel®
631xESB/
632xESB I/O
Controller Hub
/ Intel®
631xESB/
632xESB I/O
Controller Hub
timers
FEC9_0000h to FED1_FFFF
Issue request to ESI.
High SMM
FEDA_0000h to FEDB_FFFF
see Table 4-8 and Table 4-9.
Interrupt
interrupt transaction to
FEE0_0000h to FEEF_FFFFh
(not really memory space)
Route to appropriate FSB(s).
memory transaction to
FEE0_0000h to FEEF_FFFFh
Send to ESI to be master aborted.
Firmware
FF00_0000h to FFFF_FFFFh
Issue request to ESI.
High Memory
1_0000_0000 to MIR[2].LIMIT
(max FF_FFFF_FFFF)
Coherent request to main memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Coherence protocol is applied.
High MMIO
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
Route request to appropriate PCI Express port.
All others
All Others (subtractive decoding) Issue request to ESI.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
291