QG5000XSL9TH Datasheet, PDF (338/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.6.4
Note:
5.7
5.7.1
8. The “winning” xTPR register provides the values to be substituted in the
Aa[19:12]# field of the FSB Interrupt Message Transaction driven by the Intel
5000P Chipset. A[19:12]# is replaced by the logical or physical ID, depending on
the type of interrupt. The interrupt is driven onto both processor buses with the
redirection hint bit disabled (A3).
EOI
For XPF platforms using XAPIC, the EOI is a specially encoded processor bus
transaction with the interrupt vector attached. Since the EOI is not directed, the Intel
5000P Chipset will broadcast the EOI transaction to all I/O(x)APIC’s. The Intel 5000X
chipset MCH.PEXCTRL.DIS_APIC_EOI bit per PCI Express port can be used to
determine whether an EOI needs to be sent to a specific PCI Express port. EOI usage is
further described in Section 5.6.4.
The Intel 5000X chipset MCH will translate the EOI on the FSB into an EOI TLP
message type on the PCI Express/ESI ports.
I/O Interrupts
For I/O interrupts from the Intel 631xESB/632xESB I/O Controller Hub components
receive interrupts with either dedicated interrupt pins or with writes to the integrated
redirection table. The I/OxAPIC controller integrated within these components turns
these interrupts into writes destined for the processor bus with a specific address.
Interrupts triggered from an I/O device can be triggered with either a dedicated
interrupt pin or through an inbound write message from the PCI Express bus (MSI).
Note that if the interrupt is triggered by a dedicated pin, the I/OxAPIC controller in the
I/O bridge (Intel® 6700PXH 64 bit PCI Hub or ICH6 or ESB) turns this into an inbound
write. On the processor bus, the interrupt is converted to an interrupt request. Other
than a special interrupt encoding, the processor bus interrupt follows the same format
as discussed in Section 5.6.1. Therefore, to all components other than the Intel®
6700PXH 64 bit PCI Hub, ICH6 or ESB, and the processor, an interrupt is an inbound
write following the format mentioned in Section 5.6.1. Intel 5000X chipset will not
write combine or cache the APIC address space.
I/O(x)APIC’s can be configured through two mechanisms. The traditional mechanism is
the hard coded FEC0_0000 to FECF_FFFF range is used to communicate with the
IOAPIC controllers in the Intel® 6700PXH 64 bit PCI Hub, ICH6 or ESB.
The second method is to use the standard MMIO range to communicate to the Intel
6700PXH 64 bit PCI Hub. To accomplish this, the Intel® 6700PXH 64 bit PCI Hub.MBAR
and/or Intel 6700PXH 64 bit PCI Hub.XAPIC_BASE_ADDRESS_REG must be
programmed within the PCI Express device MMIO region.
Ordering
Handling interrupts as inbound writes has inherent advantages. First, there is no need
for the additional APIC bus resulting in extra pins and board routing concerns. Second,
with an out-of-band APIC bus, there are ordering concerns. Any interrupt needs to be
ordered correctly and all prior inbound writes must get flushed ahead of the interrupt.
The PCI Local Bus Specification, Revision 2.2attempts to address this by requiring all
interrupt routines to first read the PCI interrupt register. Since PCI read completions
are required to push all writes ahead of it, then all writes prior to the interrupt are
guaranteed to be flushed. However, this assumes that all drivers perform this read.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet